{"id":14,"date":"2013-07-24T16:30:28","date_gmt":"2013-07-24T15:30:28","guid":{"rendered":"http:\/\/pierofraternali.wordpress.com\/?page_id=14"},"modified":"2024-03-02T22:19:57","modified_gmt":"2024-03-02T21:19:57","slug":"publications","status":"publish","type":"page","link":"https:\/\/pilato.faculty.polimi.it\/?page_id=14","title":{"rendered":"Publications"},"content":{"rendered":"\n
2024<\/div>\n\n\n\n
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Using Artificial Intelligence to Boost Autonomy in a More Inclusive Society: The AMBRA Approach<\/div>\n
C. Pilato, A. Di Paola, S. Muraro, R. Marinelli<\/div>\n
Third International Conference of the journal \u201cScuola Democratica\u201d<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
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A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach<\/div>\n
C. Pilato, S. Banik, J. Beranek, F. Brocheton, J. Castrillon, R. Cevasco, R. Cmar, S. Curzel, F. Ferrandi, K. Friebel, A. Galizia, M. Grasso, P. Guimaraes da Silva, J. Martinovic, G. Palermo, M. Paolino, A. Parodi, A. Parodi, F. Pintus, R. Polig, D. Poulet, F. Regazzoni, B. Ringlein, R. Rocco, K. Slaninova, T. Slooff, S. Soldavini, F. Suchert, M. Tibaldi, B. Weiss, C. Hagleitner<\/div>\n
IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE 2024)<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
2023<\/div>\n\n\n\n
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Using Static Analysis for Enhancing HLS Security<\/div>\n
L. Collini, J. Ah-kiow, C. Pilato, R. Karri, B. Tan<\/div>\n
IEEE Embedded Systems Letters<\/div>\n<\/div>\n
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J<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Generating Posit-based Accelerators with High-Level Synthesis<\/div>\n
R. Murillo, A. A. Del Barrio, G. Botella, C. Pilato\n<\/div>\n
IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)<\/div>\n<\/div>\n
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J<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction<\/div>\n
J. Bhandari, A. K. Thalakkattu Moosa, B. Tan, C. Pilato, G. Gore, X. Tang, S. Temple, P.-E. Gaillardon, R. Karri\n<\/div>\n
IEEE Transactions on Very Large Scale Integration (TVLSI)<\/div>\n<\/div>\n
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J<\/div>\n<\/div>\n<\/div>\n\n\n\n
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A Survey of FPGA Optimization Methods for Data Center Energy Efficiency<\/div>\n
M. Tibaldi, C. Pilato\n<\/div>\n
IEEE Transactions on Sustainable Computing (TSUSC)<\/div>\n<\/div>\n
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J<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Towards High-Level Synthesis of Quantum Circuits<\/div>\n
C. Lu, C. Pilato, K. Basu,\n<\/div>\n
IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE 2023)<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization<\/div>\n
S. Soldavini, D. Sciuto, C. Pilato,\n<\/div>\n
Asia and South Pacific Design Automation Conference (ASP-DAC 2023)<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
2022<\/div>\n\n\n\n
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Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics<\/div>\n
S. Soldavini, K. F. A. Friebel, M. Tibaldi, G. Hempel, J. Castrillon, C. Pilato\n<\/div>\n
ACM Transactions on Reconfigurable Technology and Systems (TRETS)<\/div>\n<\/div>\n
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J<\/div>\n
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arXiv<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges<\/div>\n
L. Collini, B. Tan, C. Pilato, R. Karri,\n<\/div>\n
IEEE\/ACM International Conference on Computer-Aided Design (ICCAD 2022)<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
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High-Level Methods for Hardware IP Protections: Solutions, Trends, and Challenges<\/div>\n
C. Pilato,\n<\/div>\n
IEEE Dallas Circuits and Systems Conference (DCAS)<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Optimizing the Use of Behavioral Locking for High-Level Synthesis<\/div>\n
C. Pilato, L. Collini, L. Cassano, D. Sciuto, \nS. Garg, R. Karri\n<\/div>\n
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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Invited: High-level design methods for hardware security: Is it the right choice?<\/div>\n
C. Pilato, D. Sciuto, S. Garg, R. Karri\n\n<\/div>\n
ACM\/EDAC\/IEEE Design Automation Conference (DAC)<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
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ALICE: An Automatic Design Flow for eFPGA Redaction<\/div>\n
C. Muscari Tomajoli, L. Collini, J. Bhandari, A. Khader Thalakkattu Moosa, B. Tan, X. Tang, P.-E. Gaillardon, R. Karri, C. Pilato\n\n<\/div>\n
ACM\/EDAC\/IEEE Design Automation Conference (DAC)<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Designing ML-Resilient Locking at Register-Transfer Level<\/div>\n
D. Sisejkovic, L. Collini, B. Tan, C. Pilato, R. Karri, R. Leupers\n<\/div>\n
ACM\/EDAC\/IEEE Design Automation Conference (DAC)<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
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Dynamically-Tunable Dataflow Architectures based on Markov Queuing \nModels<\/div>\n
M. Tibaldi, G. Palermo, C. Pilato\n<\/div>\n
MDPI Electronics<\/div>\n<\/div>\n
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J<\/div>\n<\/div>\n<\/div>\n\n\n\n
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HOLL: Program Synthesis for Higher Order Logic Locking<\/div>\n
G. Takhar, R. Karri, C. Pilato, S. Roy\n<\/div>\n
International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2022)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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A Composable Design Space Exploration Framework to Optimize Behavioral Locking<\/div>\n
L. Collini, R. Karri, C. Pilato\n<\/div>\n
IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE 2022)<\/div>\n<\/div>\n
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C<\/div>\n<\/div>\n<\/div>\n\n\n\n
2021<\/div>\n\n\n\n
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A Survey on Domain-Specific Memory Architectures<\/div>\n
S. Soldavini, C. Pilato<\/div>\n
Journal of Integrated Circuits and Systems<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n
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arXiv<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics<\/div>\n
K. F. A. Friebel, S. Soldavini, G. Hempel, C. Pilato, J. Castrillon\n<\/div>\n
FPGA for HPC Workshop 2021, held in conjunction with IEEE Cluster 2021<\/div>\n<\/div>\n
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W<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n
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arXiv<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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Exploring eFPGA-based Redaction for IP Protection<\/div>\n
J. Bhandari, A. K. Thalakkattu Moosa, B. Tan, C. Pilato, G. Gore, X. Tang, S. Temple, P.-E. Gaillardon, R. Karri\n<\/div>\n
IEEE International Conference on Computer-Aided Design (ICCAD 2021)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n
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arXiv<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching<\/div>\n
D. Parravicini, D. Conficconi, E. Del Sozzo, C. Pilato, M. D. Santambrogio<\/div>\n
ACM Transactions on Embedded Computing (TECS), Special Issue on the paper accepted at CASES 2021<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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ASSURE: RTL Locking Against an Untrusted Foundry<\/div>\n
C. Pilato, A. B. Chowdhury, D. Sciuto, S. Garg, R. Karri<\/div>\n
IEEE Transactions on Very Large Scale Integration (TVLSI)<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n
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arXiv<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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High-Level Synthesis of Security Properties via Software-Level Abstractions<\/div>\n
C. Pilato, F. Regazzoni<\/div>\n
Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE)<\/div>\n<\/div>\n
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W<\/div>\n
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arXiv<\/div>\n <\/a>\n <\/div> \n
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video<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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Compiler Infrastructure for Specializing Domain-Specific Memory Templates<\/div>\n
S. Soldavini, C. Pilato<\/div>\n
Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE)<\/div>\n<\/div>\n
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W<\/div>\n
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arXiv<\/div>\n <\/a>\n <\/div> \n
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video<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications<\/div>\n
F. Ferrandi, V. G. Castellana, S. Curzel, P. Fezzardi, M. Fiorito, M. Lattuada, M. Minutoli, C. Pilato, A. Tumeo<\/div>\n
ACM\/EDAC\/IEEE Design Automation Conference (DAC)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks<\/div>\n
N. Limaye, A. B. Chowdhury, C. Pilato, M. Nabeel, O. Sinanoglu, S. Garg, R. Karri<\/div>\n
ACM\/EDAC\/IEEE Design Automation Conference (DAC)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms<\/div>\n
C. Pilato, S. Bohm, F. Brocheton, J. Castrillon, R. Cevasco, V. Cima, R. Cmar, D. Diamantopoulos, F. Ferrandi, J. Martinovic, G. Palermo, M. Paolino, A. Parodi, L. Pittaluga, D. Raho, F. Regazzoni, K. Slaninova, C. Hagleitner<\/div>\n
IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n
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arXiv<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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Vertical IP Protection of the Next-Generation Devices: Quo Vadis?<\/div>\n
S. Rai, S. Garg, C. Pilato, R. Karri, V. Herdt, R. Drechsler, E. Moussavi, D. Sisejkovic, F. Merchant, A. Kumar<\/div>\n
IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
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Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis<\/div>\n
H. Badier, C. Pilato, J. -C. Le Lann, P. Coussy, G. Gogniat<\/div>\n
IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div> \n<\/div>\n<\/div>\n\n\n\n
2020<\/div>\n\n\n\n
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Is Register Transfer Level Locking Secure?<\/div>\n
C. Karfa, R. Chouksey, C. Pilato, S. Garg, R. Karri<\/div>\n
IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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Automatic Generation of Heterogeneous SoC Architectures with Secure Communications<\/div>\n
M. Tibaldi, C. Pilato, F. Ferrandi<\/div>\n
IEEE Embedded Systems Letters<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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Agile SoC development with open ESP<\/div>\n
P. Mantovani, D. Giri, G. Di Guglielmo, L. Piccolboni, J. Zuckerman, E. G. Cota, M. Petracca, C. Pilato, L. P. Carloni<\/div>\n
IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n
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arXiv<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2019<\/div>\n\n\n\n
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CAD-base: An attack vector into the electronics supply chain<\/div>\n
K. Basu, S.M. Saeed, C. Pilato, M. Ashraf, M.T. Nabeel, K. Chakrabarty, R. Karri<\/div>\n
ACM Transactions on Design Automation of Electronic Systems<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking<\/div>\n
C. Pilato, K. Wu, S. Garg, R. Karri, F. Regazzoni<\/div>\n
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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High-Level Synthesis of Benevolent Trojans<\/div>\n
C. Pilato, K. Basu, M. Shayan, F. Regazzoni, R. Karri<\/div>\n
Design, Automation and Test in Europe Conference and Exhibition (DATE)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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Black-Hat High-Level Synthesis: Myth or Reality?<\/div>\n
C. Pilato, K. Basu, F. Regazzoni, R. Karri<\/div>\n
IEEE Transactions on Very Large Scale Integration (VLSI) Systems<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2018<\/div>\n\n\n\n
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Securing Hardware Accelerators: A New Challenge for High-Level Synthesis<\/div>\n
C. Pilato, S. Garg, K. Wu, R. Karri, F. Regazzoni<\/div>\n
IEEE Embedded Systems Letters<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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The Case for Polymorphic Registers in Dataflow Computing<\/div>\n
C.B. Ciobanu, G. Gaydadjiev, C. Pilato, D. Sciuto<\/div>\n
International Journal of Parallel Programming<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis<\/div>\n
P. Fezzardi, F. Ferrandi, C. Pilato<\/div>\n
IEEE Design and Test<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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DarkMem: Fine-grained power management of local memories for accelerators in embedded systems<\/div>\n
C. Pilato, L.P. Carloni<\/div>\n
Asia and South Pacific Design Automation Conference (ASP-DAC)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis<\/div>\n
C. Pilato<\/div>\n
International Conference on Parallel Computing (PARCO)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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TAO: techniques for algorithm-level obfuscation during high-level synthesis<\/div>\n
Christian Pilato, Francesco Regazzoni, Ramesh Karri, Siddharth Garg<\/div>\n
ACM\/EDAC\/IEEE Design Automation Conference (DAC)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2017<\/div>\n\n\n\n
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System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip<\/div>\n
C. Pilato, P. Mantovani, G. Di Guglielmo, L.P. Carloni<\/div>\n
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2016<\/div>\n\n\n\n
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A Survey and Evaluation of FPGA High-Level Synthesis Tools<\/div>\n
R. Nane, V.-M. Sima, C. Pilato, J. Choi, B. Fort, A. Canis, Y.T. Chen, H. Hsiao, S. Brown, F. Ferrandi, J. Anderson, K. Bertels<\/div>\n
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems<\/div>\n
P. Mantovani, E.G. Cota, K. Tien, C. Pilato, G. Di Guglielmo, K. Shepard, L.P. Carloni<\/div>\n
ACM\/EDAC\/IEEE Design Automation Conference (DAC)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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On the design of scalable and reusable accelerators for big data applications<\/div>\n
C. Pilato, Q. Xu, P. Mantovani, G. Di Guglielmo, L.P. Carloni<\/div>\n
ACM International Conference on Computing Frontiers (CF)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip<\/div>\n
P. Mantovani, E.G. Cota, C. Pilato, G. Di Guglielmo, L.P. Carloni<\/div>\n
International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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Scala-based domain-specific language for creating accelerator-based SoCs<\/div>\n
G.C. Durelli, F. Spada, C. Pilato, M.D. Santambrogio<\/div>\n
Reconfigurable Architectures Workshop (RAW)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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Performance Estimation of Task Graphs Based on Path Profiling<\/div>\n
M. Lattuada, C. Pilato, F. Ferrandi<\/div>\n
International Journal of Parallel Programming<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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Editorial: Special issue on innovative design methods for smart embedded systems<\/div>\n
S. Vinco, C. Pilato<\/div>\n
ACM Transactions on Embedded Computing Systems<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2015<\/div>\n\n\n\n
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FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration<\/div>\n
D. Pnevmatikatos, K. Papadimitriou, T. Becker, P. B\\”ohm, A. Brokalakis, K. Bruneel, C. Ciobanu, T. Davidson, G. Gaydadjiev, K. Heyse, W. Luk, X. Niu, I. Papaefstathiou, D. Pau, O. Pell, C. Pilato, M.D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman, E. Vansteenkiste<\/div>\n
Microprocessors and Microsystems<\/div>\n<\/div>\n
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J<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2014<\/div>\n\n\n\n
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Effective reconfigurable design: The FASTER approach<\/div>\n
D.N. Pnevmatikatos, T. Becker, A. Brokalakis, G.N. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, D. Pau, O. Pell, C. Pilato, M.D. Santambrogio, D. Sciuto, D. Stroobandt<\/div>\n
International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces<\/div>\n
A.A. Nacci, G. Bettinazzi, C. Pilato, V. Rana, M.D. Santambrogio, D. Sciuto<\/div>\n
IEEE World Forum on Internet of Things (WF-IoT)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
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PaRA-Sched: A reconfiguration-aware scheduler for reconfigurable architectures<\/div>\n
R. Cattaneo, R. Bellini, G. Durelli, C. Pilato, M.D. Santambrogio, D. Sciuto<\/div>\n
Reconfigurable Architectures Workshop (RAW)<\/div>\n<\/div>\n
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C<\/div>\n
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DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Adaptive raytracing implementation using partial dynamic reconfiguration<\/div>\n
G. Durelli, F. Spada, R. Cattaneo, C. Pilato, D. Pau, M.D. Santambrogio<\/div>\n
Reconfigurable Architectures Workshop (RAW)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
System-level memory optimization for high-level synthesis of component-based SoCs<\/div>\n
C. Pilato, P. Mantovani, G. Di Guglielmo, L.P. Carloni<\/div>\n
International Conference on Hardware\/Software Codesign and System Synthesis (CODES+ISSS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
A design methodology for compositional high-level synthesis of communication-centric SoCs<\/div>\n
G.D. Guglielmo, C. Pilato, L.P. Carloni<\/div>\n
ACM\/EDAC\/IEEE Design Automation Conference (DAC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2013<\/div>\n\n\n\n
\n
The FASTER vision for designing dynamically reconfigurable systems<\/div>\n
M.D. Santambrogio, C. Pilato, D. Pnevmatikatos, K. Papadimitriou, D. Stroobandt, D. Sciuto<\/div>\n
International Conference on IC Design and Technology (ICICDT)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
A framework for effective exploitation of partial reconfiguration in dataflow computing<\/div>\n
R. Cattaneo, X. Niu, C. Pilato, T. Becker, W. Luk, M.D. Santambrogio<\/div>\n
International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
A flexible interconnection structure for reconfigurable FPGA dataflow applications<\/div>\n
G. Durelli, A.A. Nacci, R. Cattaneo, C. Pilato, D. Sciuto, M.D. Santambrogio<\/div>\n
Reconfigurable Architectures Workshop (RAW)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems<\/div>\n
F. Cancare, C. Pilato, A. Cazzaniga, D. Sciuto, M.D. Santambrogio<\/div>\n
International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Ant colony optimization for mapping, scheduling and placing in reconfigurable systems<\/div>\n
F. Ferrandi, P.L. Lanzi, C. Pilato, D. Sciuto, A. Tumeo<\/div>\n
NASA\/ESA Conference on Adaptive Hardware and Systems (AHS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
A2B: An integrated framework for designing heterogeneous and reconfigurable systems<\/div>\n
C. Pilato, R. Cattaneo, G. Durelli, A.A. Nacci, M.D. Santambrogio, D. Sciuto<\/div>\n
NASA\/ESA Conference on Adaptive Hardware and Systems (AHS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Runtime adaptation on dataflow HPC platforms<\/div>\n
R. Cattaneo, C. Pilato, M. Mastinu, O. Kadlcek, O. Pell, M.D. Santambrogio<\/div>\n
NASA\/ESA Conference on Adaptive Hardware and Systems (AHS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs<\/div>\n
R. Cattaneo, C. Pilato, G.C. Durelli, M.D. Santambrogio, D. Sciuto<\/div>\n
International Symposium on Rapid System Prototyping (RSP)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Dataflow computing with polymorphic registers<\/div>\n
C. Ciobanu, G. Gaydadjiev, C. Pilato, D. Sciuto<\/div>\n
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
A simulation-based framework for the exploration of mapping solutions on heterogeneous MPSoCs<\/div>\n
A. Miele, C. Pilato, D. Sciuto<\/div>\n
International Journal of Embedded and Real-Time Communication Systems<\/div>\n<\/div>\n
\n
J<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2012<\/div>\n\n\n\n
\n
FASTER: Facilitating analysis and synthesis technologies for effective reconfiguration<\/div>\n
D. Pnevmatikatos, T. Becker, A. Brokalakis, K. Bruneel, G. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, O. Pell, C. Pilato, M. Robart, M.D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman<\/div>\n
Euromicro Conference on Digital System Design (DSD)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Novel design methods and a tool flow for unleashing dynamic reconfiguration<\/div>\n
K. Papadimitriou, C. Pilato, D. Pnevmatikatos, M.D. Santambrogio, C. Ciobanu, T. Todman, T. Becker, T. Davidson, X. Niu, G. Gaydadjiev, W. Luk, D. Stroobandt<\/div>\n
IEEE International Conference on Computational Science and Engineering (CSE)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
On the automatic integration of hardware accelerators into FPGA-based embedded systems<\/div>\n
C. Pilato, A. Cazzaniga, G. Durelli, A. Otero, D. Sciuto, M.D. Santambrogio<\/div>\n
International Conference on Field Programmable Logic and Applications (FPL)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
An open-source design and validation platform for reconfigurable systems<\/div>\n
A. Bonetto, A. Cazzaniga, G. Durelli, C. Pilato, D. Sciuto, M.D. Santambrogio<\/div>\n
International Conference on Field Programmable Logic and Applications (FPL)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
TaBit: A framework for task graph to bitstream generation<\/div>\n
A. Bonetto, A. Cazzaniga, G.C. Durelli, C. Pilato, D. Sciuto, M.D. Santambrogio<\/div>\n
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Smart technologies for effective reconfiguration: The FASTER approach<\/div>\n
M.D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga, G.C. Durelli, D. Sciuto<\/div>\n
International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Automatic run-time manager generation for reconfigurable MPSoC architectures<\/div>\n
G. Durelli, C. Pilato, A. Cazzaniga, D. Sciuto, M.D. Santambrogio<\/div>\n
International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
On the development of a runtime reconfigurable multicore system-on-chip<\/div>\n
A. Cazzaniga, G. Durelli, C. Pilato, D. Sciuto, M.D. Santambrogio<\/div>\n
Euromicro Conference on Digital System Design (DSD)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs<\/div>\n
A. Miele, C. Pilato, D. Sciuto<\/div>\n
International Symposium on System on Chip (SoC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2011<\/div>\n\n\n\n
\n
A runtime adaptive controller for supporting hardware components with variable latency<\/div>\n
C. Pilato, V.G. Castellana, S. Lovergine, F. Ferrandi<\/div>\n
NASA\/ESA Conference on Adaptive Hardware and Systems (AHS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Combined architecture and hardening techniques exploration for reliable embedded system design<\/div>\n
C. Bolchini, A. Miele, C. Pilato<\/div>\n
ACM Great Lakes Symposium on VLSI (GLSVLSI)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
A design methodology for the automatic sizing of standard-cell libraries<\/div>\n
C. Pilato, F. Ferrandi, D. Pandini<\/div>\n
ACM Great Lakes Symposium on VLSI (GLSVLSI)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Synaptic project: Regularity applied to enhance manufacturability and yield at several abstraction levels (invited paper)<\/div>\n
M. Elhoj, A. Reis, R. Ribas, F. Ferrandi, C. Pilato, F. Moll, M. Miranda, P. Dobrovolny, N. Woolaway, A. Grasset, P. Bonnot, G. Desoli, D. Pandini<\/div>\n
Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms (ERDIAP)<\/div>\n<\/div>\n
\n
C<\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Evaluating static CMOS complex cells in technology mapping<\/div>\n
C. Pilato, F. Ferrandi, D. Pandini<\/div>\n
Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms (ERDIAP)<\/div>\n<\/div>\n
\n
C<\/div>\n<\/div>\n<\/div>\n\n\n\n
2010<\/div>\n\n\n\n
\n
The hArtes CarLab: A new approach to advanced algorithms development for automotive audio<\/div>\n
S. Cecchi, A. Primavera, F. Piazza, F. Bettarelli, E. Ciavattini, R. Toppi, J.G.F. Coutinho, W. Luk, C. Pilato, F. Ferrandi, V.M. Sima, K. Bertels<\/div>\n
Audio Engineering Society Convention (AES)<\/div>\n<\/div>\n
\n
C<\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
HArtes: Hardware-software codesign for heterogeneous multicore platforms<\/div>\n
K. Bertels, V.-M. Sima, Y. Yankova, G. Kuzmanov, W. Luk, G. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada, D. Sciuto, A. Michelotti<\/div>\n
IEEE Micro<\/div>\n<\/div>\n
\n
J<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems<\/div>\n
F. Ferrandi, P.L. Lanzi, C. Pilato, D. Sciuto, A. Tumeo<\/div>\n
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems<\/div>\n<\/div>\n
\n
J<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs<\/div>\n
F. Ferrandi, C. Pilato, D. Sciuto, A. Tumeo<\/div>\n
Asia and South Pacific Design Automation Conference (ASP-DAC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
A fast heuristic for extending standard cell libraries with regular macro cells<\/div>\n
C. Pilato, F. Ferrandi, D. Pandini<\/div>\n
IEEE Annual Symposium on VLSI (ISVLSI)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2009<\/div>\n\n\n\n
\n
Mapping pipelined applications onto heterogeneous embedded systems: A Bayesian optimization algorithm based approach<\/div>\n
A. Tumeo, M. Branca, L. Camerini, C. Pilato, P.L. Lanzi, F. Ferrandi, D. Sciuto<\/div>\n
IEEE\/ACM International Conference on Hardware\/Software-Co-Design and System Synthesis (CODES+ISSS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems<\/div>\n
M. Branca, L. Camerini, F. Ferrandi, P.L. Lanzi, C. Pilato, D. Sciuto, A. Tumeo<\/div>\n
Annual Genetic and Evolutionary Computation Conference (GECCO)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
HW\/SW methodologies for synchronization in FPGA<\/div>\n
A. Tumeo, C. Pilato, G. Palermo, F. Ferrandi, D. Sciuto<\/div>\n
ACM SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Performance estimation for task graphs combining sequential path profiling and control dependence regions<\/div>\n
F. Ferrandi, M. Lattuada, C. Pilato, A. Tumeo<\/div>\n
IEEE\/ACM International Conference on Formal Methods and Models for Co-Design (MEMOCODE)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Performance modeling of parallel applications on MPSoCs<\/div>\n
M. Lattuada, C. Pilato, A. Tumeo, F. Ferrandi<\/div>\n
International Symposium on System-on-Chip (SoC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2008<\/div>\n\n\n\n
\n
Improving evolutionary exploration to area-time optimization of FPGA designs<\/div>\n
C. Pilato, A. Tumeo, G. Palermo, F. Ferrandi, P.L. Lanzi, D. Sciuto<\/div>\n
Journal of Systems Architecture<\/div>\n<\/div>\n
\n
J<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
A multi-objective genetic algorithm for design space exploration in high-level synthesis<\/div>\n
F. Ferrandi, P.L. Lanzi, D. Loiacono, C. Pilato, D. Sciuto<\/div>\n
IEEE Computer Society Annual Symposium on VLSI (ISVLSI)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis<\/div>\n
C. Pilato, D. Loiacono, F. Ferrandi, P.L. Lanzi, D. Sciuto<\/div>\n
IEEE Congress on Evolutionary Computation (CEC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems<\/div>\n
A. Tumeo, C. Pilato, F. Ferrandi, D. Sciuto, P.L. Lanzi<\/div>\n
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
2007<\/div>\n\n\n\n
\n
An evolutionary approach to area-time optimization of FPGA designs<\/div>\n
F. Ferrandi, P.L. Lanzi, G. Palermo, C. Pilato, D. Sciuto, A. Tumeo<\/div>\n
International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n\n\n\n
\n
Fitness inheritance in evolutionary and multi-objective high-level synthesis<\/div>\n
C. Pilato, G. Palermo, A. Tumeo, F. Ferrandi, D. Sciuto, P.L. Lanzi<\/div>\n
IEEE Congress on Evolutionary Computation (CEC)<\/div>\n<\/div>\n
\n
C<\/div>\n
\n \n
DOI<\/div>\n <\/a>\n <\/div>\n<\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

2024 Using Artificial Intelligence to Boost Autonomy in a More Inclusive Society: The AMBRA Approach C. Pilato, A. Di Paola, S. Muraro, R. Marinelli Third International Conference of the journal \u201cScuola Democratica\u201d C A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach C. Pilato, S. Banik, J. Beranek, F. Brocheton, … Continue reading “Publications”<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":4,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-14","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/14","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=14"}],"version-history":[{"count":216,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/14\/revisions"}],"predecessor-version":[{"id":1269,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/14\/revisions\/1269"}],"wp:attachment":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=14"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}