{"id":549,"date":"2020-04-14T18:20:12","date_gmt":"2020-04-14T17:20:12","guid":{"rendered":"http:\/\/pilato.faculty.polimi.it\/?page_id=549"},"modified":"2020-04-14T18:20:12","modified_gmt":"2020-04-14T17:20:12","slug":"seminars","status":"publish","type":"page","link":"https:\/\/pilato.faculty.polimi.it\/?page_id=549","title":{"rendered":"Seminars"},"content":{"rendered":"\n<p>\u201cHardware security and high-level synthesis: the good, the bad and the ugly\u201d at Columbia University, New York, NY, USA, November 9, 2018<\/p>\n\n\n\n<p>\u201cOptimizing private local memories in heterogeneous architectures\u201d at University of California Irvine (UCI), Irvine, CA, USA, June 14, 2017<\/p>\n\n\n\n<p>\u201cDesigning and Optimizing Hardware Accelerators with Private Local Memories\u201d at Swiss Federal Institute of Tech- nology (ETH), Zurich, Switzerland, May 24, 2017<\/p>\n\n\n\n<p>\u201cTaintHLS: Enabling Dynamic Information Flow Tracking in Hardware Accelerators\u201d at New York University (NYU), New York, NY, USA, November 2, 2016<\/p>\n\n\n\n<p>\u201cSystem-Level Memory Optimization for Heterogeneous System-on-Chip Architectures\u201d at Universit\u00e0 della Svizzera italiana (USI), Lugano, Switzerland, January 16, 2015<\/p>\n\n\n\n<p>\u201cDesign Challenges and Techniques for Heterogeneous Reconfigurable Systems\u201d at Ecole Polytechnique, Montr\u00e9al, QC, Canada, September 26, 2013<\/p>\n\n\n\n<p>\u201cOn the Automatic Synthesis of Hardware Accelerators for Improving Embedded Systems\u201d at Columbia University, New York, NY, USA, May 23, 2013<\/p>\n\n\n\n<p>\u201cAccelerating research in reconfigurable computing: the FASTER approach\u201d at Massachusetts Institute of Technology(MIT), Boston, MA, USA, May 22, 2013<\/p>\n","protected":false},"excerpt":{"rendered":"<p>\u201cHardware security and high-level synthesis: the good, the bad and the ugly\u201d at Columbia University, New York, NY, USA, November 9, 2018 \u201cOptimizing private local memories in heterogeneous architectures\u201d at University of California Irvine (UCI), Irvine, CA, USA, June 14, 2017 \u201cDesigning and Optimizing Hardware Accelerators with Private Local Memories\u201d at Swiss Federal Institute of &hellip; <a href=\"https:\/\/pilato.faculty.polimi.it\/?page_id=549\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;Seminars&#8221;<\/span><\/a><\/p>\n","protected":false},"author":11,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-549","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/549","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/users\/11"}],"replies":[{"embeddable":true,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=549"}],"version-history":[{"count":1,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/549\/revisions"}],"predecessor-version":[{"id":550,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/549\/revisions\/550"}],"wp:attachment":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=549"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}