{"id":7,"date":"2011-02-10T15:08:41","date_gmt":"2011-02-10T14:08:41","guid":{"rendered":"http:\/\/pierofraternali.wordpress.com\/?page_id=2"},"modified":"2024-03-02T22:16:46","modified_gmt":"2024-03-02T21:16:46","slug":"about","status":"publish","type":"page","link":"https:\/\/pilato.faculty.polimi.it\/","title":{"rendered":"About me"},"content":{"rendered":"\n
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Associate Professor
<\/strong>Dipartimento di Elettronica, Informazione e Bioingegneria<\/a> — Politecnico di Milano, Italy<\/a><\/p>\n\n\n\n

Research interests<\/strong>: high-level synthesis, FPGA, and system-on-chip architectures with emphasis on memory and security aspects.<\/p>\n\n\n\n

Memberships<\/strong>: IEEE Senior Member, ACM Senior Member, HiPEAC Member.<\/p>\n<\/div>\n\n\n\n

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DBLP publications, Google Scholar, LinkedIn<\/figcaption><\/figure>\n<\/div>\n<\/div>\n\n\n\n

More News<\/strong>: here<\/a><\/p>\n\n\n\n

\n
\nMarch<\/span>\n2024<\/span><\/div>\n
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Publication<\/div>\n
New contribution accepted at the third International Conference of the journal \u201cScuola Democratica\u201d: Using Artificial Intelligence to Boost Autonomy in a More Inclusive Society: The AMBRA Approach<\/span>. This is a joint work with Fondazione Artos.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nOctober<\/span>\n2023<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted at IEEE ESL: Using Static Analysis for Enhancing HLS Security<\/span>. This is a joint work with NYU and University of Calgary.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJuly<\/span>\n2023<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted at IEEE TCAS-I: Generating Posit-based Accelerators with High-Level Synthesis<\/span>. This is a joint work with UCM.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJuly<\/span>\n2023<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted at IEEE TVLSI: Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction<\/span>. This is a joint work with NYU, University of Calgary, and University of Utah.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMay<\/span>\n2023<\/span><\/div>\n
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TPC Work<\/div>\n
I will be serving as Track Co-Chair at ICCAD 2023 (track “High-Level, Behavioral, and Logic Synthesis and Optimization”).<\/div>\n<\/div><\/div>\n\n\n\n
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\nMay<\/span>\n2023<\/span><\/div>\n
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Conference Organization<\/div>\n
I will be serving as PhD Forum Chair (DEC member) at DATE 2024.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMarch<\/span>\n2023<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted at IEEE TSUSC: A Survey of FPGA Optimization Methods for Data Center Energy Efficiency<\/span>.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMarch<\/span>\n2023<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as a TPC member at CASES 2023<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJanuary<\/span>\n2023<\/span><\/div>\n
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Conference Organization<\/div>\n
I will be serving as Program Chair at SAMOS XXIII.<\/div>\n<\/div><\/div>\n\n\n\n
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\nDecember<\/span>\n2022<\/span><\/div>\n
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Conference Organization<\/div>\n
I will be serving as Program Chair at ICCD 2023.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nNovember<\/span>\n2022<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted for presentation at DATE 2023: Towards High-Level Synthesis of Quantum Circuits.<\/span> This is a collaboration with UT Dallas.<\/div>\n<\/div><\/div>\n\n\n\n
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\nSeptember<\/span>\n2022<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted for presentation at ASPDAC 2023: Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization.<\/span><\/div>\n<\/div><\/div>\n\n\n\n
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\nAugust<\/span>\n2022<\/span><\/div>\n
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Publication<\/div>\n
New paper accepted at ACM TRETS: Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics<\/span>. This is a joint work with TU Dresden.<\/div>\n<\/div><\/div>\n\n\n\n
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\nAugust<\/span>\n2022<\/span><\/div>\n
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Conference Organization<\/div>\n
I will be serving as Vice General Chair at FCCM 2023.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJuly<\/span>\n2022<\/span><\/div>\n
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Conference Organization<\/div>\n
Together with Akash Kumar (TU Dresden), we will organize a special session titled “Hardware Security Through Reconfigurability: Attacks, Defenses, and Challenges” at ICCAD 2022.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJune<\/span>\n2022<\/span><\/div>\n
\n
Conference Organization<\/div>\n
Together with Jeronimo Castrillon (TUD), Christian Plessl (Paderborn Center for Parallel Computing), Chris Kachris (inaccel), Dionysios Diamantopoulos (IBM), Burkhard Ringlein (IBM, and Christoph Hagleitner (IBM), we will be organizing a Workshop “DevOps Support for Cloud FPGA platforms” at FPL 2022.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJune<\/span>\n2022<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as Track Co-Chair at ICCAD 2022 (track “High-Level, Behavioral, and Logic Synthesis and Optimization”).<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMay<\/span>\n2022<\/span><\/div>\n
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TPC Work<\/div>\n
I will be serving as a TPC member at FPT 2022<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMay<\/span>\n2022<\/span><\/div>\n
\n
Conference Organization<\/div>\n
I will be serving as PhD Forum Chair (DEC member) at DATE 2023.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMay<\/span>\n2022<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as Topic Chair at DATE 2023 (topic “System-Level Design Methodologies and High-Level Synthesis”).<\/div>\n<\/div><\/div>\n\n\n\n
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\nMay<\/span>\n2022<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted at IEEE TCAD: Optimizing the Use of Behavioral Locking for High-Level Synthesis<\/span>. This is a joint work with NYU.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMay<\/span>\n2022<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as a TPC member at ASPDAC 2023<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nApril<\/span>\n2022<\/span><\/div>\n
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TPC Work<\/div>\n
I will be serving as Track Chair at CASES 2022 (topic ” “Architectures, Compilers, System-level Design”).<\/div>\n<\/div><\/div>\n\n\n\n
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\nMarch<\/span>\n2022<\/span><\/div>\n
\n
Conference Organization<\/div>\n
I will be the Program Chair of ICCD 2022.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMarch<\/span>\n2022<\/span><\/div>\n
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Conference Organization<\/div>\n
I will organize a special session titled “Security during system level design: Small step or giant leap?” at DAC 2022.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMarch<\/span>\n2022<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as a TPC member at ICCAD 2022<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nFebruary<\/span>\n2022<\/span><\/div>\n
\n
Publication<\/div>\n
Two new papers accepted for presentation at DAC 2022: Designing ML-Resilient Locking at Register-Transfer Level<\/span> (joint work with RWTH Aachen University, University of Calgary, and NYU) and ALICE: An Automatic Design Flow for eFPGA Redaction<\/span> (joint work with University of Calgary, NYU, and University of Utah).<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nFebruary<\/span>\n2022<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted at MDPI Electronics: Dynamically-Tunable Dataflow Architectures based on Markov Queuing Models<\/span><\/div>\n<\/div><\/div>\n\n\n\n
\n
\nFebruary<\/span>\n2022<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as a TPC member at CASES 2022<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJanuary<\/span>\n2022<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as Tutorial Committee Member at SC 2022<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nDecember<\/span>\n2021<\/span><\/div>\n
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Publication<\/div>\n
New paper accepted for presentation at TACAS 2022: HOLL: Program Synthesis for Higher Order Logic Locking<\/span>. This is a joint work with IIT Kanpur and NYU.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nNovember<\/span>\n2021<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted for presentation at DATE 2022: A Composable Design Space Exploration Framework to Optimize Behavioral Locking<\/span>.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nNovember<\/span>\n2021<\/span><\/div>\n
\n
Conference Organization<\/div>\n
Together with Jeronimo Castrillon (TUD) and Christoph Hagleitner (IBM), we will be organizing a Workshop “Data-driven applications for industrial and societal challenges: Problems, methods, and computing platforms” at DATE 2022.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nOctober<\/span>\n2021<\/span><\/div>\n
\n
Achievements<\/div>\n
Our RTL locking ASSURE<\/a> tool is now part of the IEEE CEDA DATC Robust Design Flow (RDF)<\/a><\/div>\n<\/div><\/div>\n\n\n\n
\n
\nOctober<\/span>\n2021<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as Track Chair at DAC 2022 (topic “RTL\/Logic Level and High-level Synthesis”).<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJuly<\/span>\n2021<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted at the Journal of Integrated Circuits and Systems: A Survey on Domain-Specific Memory Architectures<\/span>.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJuly<\/span>\n2021<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted for presentation at HPC-FPGA 2021: From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics<\/span>. This is a joint work with TU Dresden.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJuly<\/span>\n2021<\/span><\/div>\n
\n
Conference Organization<\/div>\n
Together with Francesco Regazzoni (USI), Katerina Slaninova (IT4I), and Antonella Galizia (CIMA), we will be organizing the PhD Summer School “Extreme-scale big data analytics and scientific computing on heterogeneous platforms” at Lake Como in 2022.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJuly<\/span>\n2021<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted for presentation at ICCAD 2021: Exploring eFPGA-based Redaction for IP Protection<\/span>. This is a joint work with New York University and University of Utah.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJuly<\/span>\n2021<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted at ACM TECS and for presentation at CASES 2021: CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching<\/span>.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJune<\/span>\n2021<\/span><\/div>\n
\n
Conference Organization<\/div>\n
Together with Francesco Regazzoni (USI), Jeronimo Castrillon (TU Dresden), and Antonella Galizia (CIMA), we will be organizing the EVEREST Workshop on Design and Programming High-performance, distributed, reconfigurable and heterogeneous platforms for extreme-scale analytics at HIPEAC 2022.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJune<\/span>\n2021<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as Topic Co-Chair at DATE 2022 (topic “System-Level Design Methodologies and High-Level Synthesis”).<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nApril<\/span>\n2021<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted at IEEE TVLSI: ASSURE: RTL Locking Against an Untrusted Foundry<\/span>. This is a joint work with New York University.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMarch<\/span>\n2021<\/span><\/div>\n
\n
TPC Work<\/div>\n
I will be serving as a TPC member at ICCAD 2021<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nMarch<\/span>\n2021<\/span><\/div>\n
\n
Editorial activities<\/div>\n
I will be lead guest editor of the ACM TODAES special issue on High-Level Synthesis for FPGA: Next-Generation Technologies and Applications<\/i>. The GE team includes Zhenman Fang (Simon Fraser University), Yuko Hara-Azumi (Tokyo Institute of Technology), and Jim Hwang (Xilinx, Inc).<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nFebruary<\/span>\n2021<\/span><\/div>\n
\n
Publication<\/div>\n
New paper accepted for presentation at DAC 2021: Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks<\/span>. This is a joint work with New York University and New York University Abu Dhabi.<\/div>\n<\/div><\/div>\n\n\n\n
\n
\nJanuary<\/span>\n2021<\/span><\/div>\n
\n
Invited presentation<\/div>\n
I will give a keynote at RAPIDO 2021 (HiPEAC Workshop).<\/div>\n<\/div><\/div>\n","protected":false},"excerpt":{"rendered":"

Associate ProfessorDipartimento di Elettronica, Informazione e Bioingegneria — Politecnico di Milano, Italy Research interests: high-level synthesis, FPGA, and system-on-chip architectures with emphasis on memory and security aspects. Memberships: IEEE Senior Member, ACM Senior Member, HiPEAC Member. More News: here March 2024 Publication New contribution accepted at the third International Conference of the journal \u201cScuola Democratica\u201d: … Continue reading “About me”<\/span><\/a><\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":1,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-7","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/7","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=7"}],"version-history":[{"count":122,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/7\/revisions"}],"predecessor-version":[{"id":1266,"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=\/wp\/v2\/pages\/7\/revisions\/1266"}],"wp:attachment":[{"href":"https:\/\/pilato.faculty.polimi.it\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=7"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}