Dipartimento di Elettronica, Informazione e Bioingegneria — Politecnico di Milano, Italy
Research interests: high-level synthesis, reconfigurable systems, and system-on-chip architectures with emphasis on memory and security aspects.
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New paper accepted at IEEE TVLSI: ASSURE: RTL Locking Against an Untrusted Foundry. This is a joint work with New York University.
I will be serving as a TPC member at ICCAD 2021
I will be lead guest editor of the ACM TODAES special issue on High-Level Synthesis for FPGA: Next-Generation Technologies and Applications. The GE team includes Zhenman Fang (Simon Fraser University), Yuko Hara-Azumi (Tokyo Institute of Technology), and Jim Hwang (Xilinx, Inc).
New paper accepted for presentation at DAC 2021: Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. This is a joint work with New York University and New York University Abu Dhabi.
I will give a keynote at RAPIDO 2021 (HiPEAC Workshop).