Research interests: high-level synthesis, reconfigurable systems, and system-on-chip architectures with emphasis on memory and security aspects.
- November 2020: New IP paper accepted for presentation at DATE 2021 “Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis.” This is a joint work with Université de Bretagne-Sud – Lab-STICC and ENSTA Bretagne – Lab-STICC.
- October 2020: I will be serving as a TPC member at DAC 2021 (track “EDA4. RTL/Logic Level and High-Level Synthesis”)
- August 2020: New invited paper accepted for presentation at ICCAD 2020 “Agile SoC Development with Open ESP.” This is a joint work with Columbia University.
- August 2020: I will be the Scientific Coordinator of the H2020 EVEREST project (more details here)
- June 2020: New paper accepted at IEEE ESL: “Automatic Generation of Heterogeneous SoC Architectures with Secure Communications“
- June 2020: Now serving as Associate Editor for IEEE Access
- April 2020: I will be serving as a TPC member at ICCAD 2020 (track “High-Level, Behavioral, and Logic Synthesis and Optimization”)
- March 2020: I will be serving as Topic Co-Chair at DATE 2021 (track “System-Level Design Methodologies and High-Level Synthesis”)