“Hardware security and high-level synthesis: the good, the bad and the ugly” at Columbia University, New York, NY, USA, November 9, 2018

“Optimizing private local memories in heterogeneous architectures” at University of California Irvine (UCI), Irvine, CA, USA, June 14, 2017

“Designing and Optimizing Hardware Accelerators with Private Local Memories” at Swiss Federal Institute of Tech- nology (ETH), Zurich, Switzerland, May 24, 2017

“TaintHLS: Enabling Dynamic Information Flow Tracking in Hardware Accelerators” at New York University (NYU), New York, NY, USA, November 2, 2016

“System-Level Memory Optimization for Heterogeneous System-on-Chip Architectures” at Università della Svizzera italiana (USI), Lugano, Switzerland, January 16, 2015

“Design Challenges and Techniques for Heterogeneous Reconfigurable Systems” at Ecole Polytechnique, Montréal, QC, Canada, September 26, 2013

“On the Automatic Synthesis of Hardware Accelerators for Improving Embedded Systems” at Columbia University, New York, NY, USA, May 23, 2013

“Accelerating research in reconfigurable computing: the FASTER approach” at Massachusetts Institute of Technology(MIT), Boston, MA, USA, May 22, 2013