Publications

2024

Using Artificial Intelligence to Boost Autonomy in a More Inclusive Society: The AMBRA Approach

C. Pilato, A. Di Paola, S. Muraro, R. Marinelli

Third International Conference of the journal “Scuola Democratica”

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A System Development Kit for Big Data Applications on FPGA-based Clusters: The EVEREST Approach

C. Pilato, S. Banik, J. Beranek, F. Brocheton, J. Castrillon, R. Cevasco, R. Cmar, S. Curzel, F. Ferrandi, K. Friebel, A. Galizia, M. Grasso, P. Guimaraes da Silva, J. Martinovic, G. Palermo, M. Paolino, A. Parodi, A. Parodi, F. Pintus, R. Polig, D. Poulet, F. Regazzoni, B. Ringlein, R. Rocco, K. Slaninova, T. Slooff, S. Soldavini, F. Suchert, M. Tibaldi, B. Weiss, C. Hagleitner

IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE 2024)

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2023

Using Static Analysis for Enhancing HLS Security

L. Collini, J. Ah-kiow, C. Pilato, R. Karri, B. Tan

IEEE Embedded Systems Letters

J

Generating Posit-based Accelerators with High-Level Synthesis

R. Murillo, A. A. Del Barrio, G. Botella, C. Pilato

IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)

J

Not All Fabrics Are Created Equal: Exploring eFPGA Parameters For IP Redaction

J. Bhandari, A. K. Thalakkattu Moosa, B. Tan, C. Pilato, G. Gore, X. Tang, S. Temple, P.-E. Gaillardon, R. Karri

IEEE Transactions on Very Large Scale Integration (TVLSI)

J

A Survey of FPGA Optimization Methods for Data Center Energy Efficiency

M. Tibaldi, C. Pilato

IEEE Transactions on Sustainable Computing (TSUSC)

J

Towards High-Level Synthesis of Quantum Circuits

C. Lu, C. Pilato, K. Basu,

IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE 2023)

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Iris: Automatic Generation of Efficient Data Layouts for High Bandwidth Utilization

S. Soldavini, D. Sciuto, C. Pilato,

Asia and South Pacific Design Automation Conference (ASP-DAC 2023)

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2022

Automatic Creation of High-Bandwidth Memory Architectures from Domain-Specific Languages: The Case of Computational Fluid Dynamics

S. Soldavini, K. F. A. Friebel, M. Tibaldi, G. Hempel, J. Castrillon, C. Pilato

ACM Transactions on Reconfigurable Technology and Systems (TRETS)

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Reconfigurable Logic for Hardware IP Protection: Opportunities and Challenges

L. Collini, B. Tan, C. Pilato, R. Karri,

IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2022)

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High-Level Methods for Hardware IP Protections: Solutions, Trends, and Challenges

C. Pilato,

IEEE Dallas Circuits and Systems Conference (DCAS)

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Optimizing the Use of Behavioral Locking for High-Level Synthesis

C. Pilato, L. Collini, L. Cassano, D. Sciuto, S. Garg, R. Karri

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

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Invited: High-level design methods for hardware security: Is it the right choice?

C. Pilato, D. Sciuto, S. Garg, R. Karri

ACM/EDAC/IEEE Design Automation Conference (DAC)

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ALICE: An Automatic Design Flow for eFPGA Redaction

C. Muscari Tomajoli, L. Collini, J. Bhandari, A. Khader Thalakkattu Moosa, B. Tan, X. Tang, P.-E. Gaillardon, R. Karri, C. Pilato

ACM/EDAC/IEEE Design Automation Conference (DAC)

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Designing ML-Resilient Locking at Register-Transfer Level

D. Sisejkovic, L. Collini, B. Tan, C. Pilato, R. Karri, R. Leupers

ACM/EDAC/IEEE Design Automation Conference (DAC)

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Dynamically-Tunable Dataflow Architectures based on Markov Queuing Models

M. Tibaldi, G. Palermo, C. Pilato

MDPI Electronics

J

HOLL: Program Synthesis for Higher Order Logic Locking

G. Takhar, R. Karri, C. Pilato, S. Roy

International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2022)

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A Composable Design Space Exploration Framework to Optimize Behavioral Locking

L. Collini, R. Karri, C. Pilato

IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE 2022)

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2021

A Survey on Domain-Specific Memory Architectures

S. Soldavini, C. Pilato

Journal of Integrated Circuits and Systems

J

From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics

K. F. A. Friebel, S. Soldavini, G. Hempel, C. Pilato, J. Castrillon

FPGA for HPC Workshop 2021, held in conjunction with IEEE Cluster 2021

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Exploring eFPGA-based Redaction for IP Protection

J. Bhandari, A. K. Thalakkattu Moosa, B. Tan, C. Pilato, G. Gore, X. Tang, S. Temple, P.-E. Gaillardon, R. Karri

IEEE International Conference on Computer-Aided Design (ICCAD 2021)

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CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching

D. Parravicini, D. Conficconi, E. Del Sozzo, C. Pilato, M. D. Santambrogio

ACM Transactions on Embedded Computing (TECS), Special Issue on the paper accepted at CASES 2021

J

ASSURE: RTL Locking Against an Untrusted Foundry

C. Pilato, A. B. Chowdhury, D. Sciuto, S. Garg, R. Karri

IEEE Transactions on Very Large Scale Integration (TVLSI)

J

High-Level Synthesis of Security Properties via Software-Level Abstractions

C. Pilato, F. Regazzoni

Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE)

W

Compiler Infrastructure for Specializing Domain-Specific Memory Templates

S. Soldavini, C. Pilato

Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE)

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Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications

F. Ferrandi, V. G. Castellana, S. Curzel, P. Fezzardi, M. Fiorito, M. Lattuada, M. Minutoli, C. Pilato, A. Tumeo

ACM/EDAC/IEEE Design Automation Conference (DAC)

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Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks

N. Limaye, A. B. Chowdhury, C. Pilato, M. Nabeel, O. Sinanoglu, S. Garg, R. Karri

ACM/EDAC/IEEE Design Automation Conference (DAC)

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EVEREST: A design environment for extreme-scale big data analytics on heterogeneous platforms

C. Pilato, S. Bohm, F. Brocheton, J. Castrillon, R. Cevasco, V. Cima, R. Cmar, D. Diamantopoulos, F. Ferrandi, J. Martinovic, G. Palermo, M. Paolino, A. Parodi, L. Pittaluga, D. Raho, F. Regazzoni, K. Slaninova, C. Hagleitner

IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE)

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Vertical IP Protection of the Next-Generation Devices: Quo Vadis?

S. Rai, S. Garg, C. Pilato, R. Karri, V. Herdt, R. Drechsler, E. Moussavi, D. Sisejkovic, F. Merchant, A. Kumar

IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE)

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Opportunistic IP Birthmarking using Side Effects of Code Transformations on High-Level Synthesis

H. Badier, C. Pilato, J. -C. Le Lann, P. Coussy, G. Gogniat

IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE)

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2020

Is Register Transfer Level Locking Secure?

C. Karfa, R. Chouksey, C. Pilato, S. Garg, R. Karri

IEEE Design, Automation and Test in Europe Conference and Exhibition (DATE)

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Automatic Generation of Heterogeneous SoC Architectures with Secure Communications

M. Tibaldi, C. Pilato, F. Ferrandi

IEEE Embedded Systems Letters

J

Agile SoC development with open ESP

P. Mantovani, D. Giri, G. Di Guglielmo, L. Piccolboni, J. Zuckerman, E. G. Cota, M. Petracca, C. Pilato, L. P. Carloni

IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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2019

CAD-base: An attack vector into the electronics supply chain

K. Basu, S.M. Saeed, C. Pilato, M. Ashraf, M.T. Nabeel, K. Chakrabarty, R. Karri

ACM Transactions on Design Automation of Electronic Systems

J

TaintHLS: High-Level Synthesis for Dynamic Information Flow Tracking

C. Pilato, K. Wu, S. Garg, R. Karri, F. Regazzoni

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

J

High-Level Synthesis of Benevolent Trojans

C. Pilato, K. Basu, M. Shayan, F. Regazzoni, R. Karri

Design, Automation and Test in Europe Conference and Exhibition (DATE)

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Black-Hat High-Level Synthesis: Myth or Reality?

C. Pilato, K. Basu, F. Regazzoni, R. Karri

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

J

2018

Securing Hardware Accelerators: A New Challenge for High-Level Synthesis

C. Pilato, S. Garg, K. Wu, R. Karri, F. Regazzoni

IEEE Embedded Systems Letters

J

The Case for Polymorphic Registers in Dataflow Computing

C.B. Ciobanu, G. Gaydadjiev, C. Pilato, D. Sciuto

International Journal of Parallel Programming

J

Enabling Automated Bug Detection for IP-Based Designs Using High-Level Synthesis

P. Fezzardi, F. Ferrandi, C. Pilato

IEEE Design and Test

J

DarkMem: Fine-grained power management of local memories for accelerators in embedded systems

C. Pilato, L.P. Carloni

Asia and South Pacific Design Automation Conference (ASP-DAC)

C

Bridging the Gap between Software and Hardware Designers Using High-Level Synthesis

C. Pilato

International Conference on Parallel Computing (PARCO)

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TAO: techniques for algorithm-level obfuscation during high-level synthesis

Christian Pilato, Francesco Regazzoni, Ramesh Karri, Siddharth Garg

ACM/EDAC/IEEE Design Automation Conference (DAC)

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2017

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip

C. Pilato, P. Mantovani, G. Di Guglielmo, L.P. Carloni

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

J

2016

A Survey and Evaluation of FPGA High-Level Synthesis Tools

R. Nane, V.-M. Sima, C. Pilato, J. Choi, B. Fort, A. Canis, Y.T. Chen, H. Hsiao, S. Brown, F. Ferrandi, J. Anderson, K. Bertels

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

J

An FPGA-based infrastructure for fine-grained DVFS analysis in high-performance embedded systems

P. Mantovani, E.G. Cota, K. Tien, C. Pilato, G. Di Guglielmo, K. Shepard, L.P. Carloni

ACM/EDAC/IEEE Design Automation Conference (DAC)

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On the design of scalable and reusable accelerators for big data applications

C. Pilato, Q. Xu, P. Mantovani, G. Di Guglielmo, L.P. Carloni

ACM International Conference on Computing Frontiers (CF)

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Handling large data sets for high-performance embedded applications in heterogeneous systems-on-chip

P. Mantovani, E.G. Cota, C. Pilato, G. Di Guglielmo, L.P. Carloni

International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES)

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Scala-based domain-specific language for creating accelerator-based SoCs

G.C. Durelli, F. Spada, C. Pilato, M.D. Santambrogio

Reconfigurable Architectures Workshop (RAW)

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Performance Estimation of Task Graphs Based on Path Profiling

M. Lattuada, C. Pilato, F. Ferrandi

International Journal of Parallel Programming

J

Editorial: Special issue on innovative design methods for smart embedded systems

S. Vinco, C. Pilato

ACM Transactions on Embedded Computing Systems

J

2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration

D. Pnevmatikatos, K. Papadimitriou, T. Becker, P. B\”ohm, A. Brokalakis, K. Bruneel, C. Ciobanu, T. Davidson, G. Gaydadjiev, K. Heyse, W. Luk, X. Niu, I. Papaefstathiou, D. Pau, O. Pell, C. Pilato, M.D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman, E. Vansteenkiste

Microprocessors and Microsystems

J

2014

Effective reconfigurable design: The FASTER approach

D.N. Pnevmatikatos, T. Becker, A. Brokalakis, G.N. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, D. Pau, O. Pell, C. Pilato, M.D. Santambrogio, D. Sciuto, D. Stroobandt

International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)

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A SystemC-based framework for the simulation of appliances networks in energy-aware smart spaces

A.A. Nacci, G. Bettinazzi, C. Pilato, V. Rana, M.D. Santambrogio, D. Sciuto

IEEE World Forum on Internet of Things (WF-IoT)

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PaRA-Sched: A reconfiguration-aware scheduler for reconfigurable architectures

R. Cattaneo, R. Bellini, G. Durelli, C. Pilato, M.D. Santambrogio, D. Sciuto

Reconfigurable Architectures Workshop (RAW)

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Adaptive raytracing implementation using partial dynamic reconfiguration

G. Durelli, F. Spada, R. Cattaneo, C. Pilato, D. Pau, M.D. Santambrogio

Reconfigurable Architectures Workshop (RAW)

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System-level memory optimization for high-level synthesis of component-based SoCs

C. Pilato, P. Mantovani, G. Di Guglielmo, L.P. Carloni

International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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A design methodology for compositional high-level synthesis of communication-centric SoCs

G.D. Guglielmo, C. Pilato, L.P. Carloni

ACM/EDAC/IEEE Design Automation Conference (DAC)

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2013

The FASTER vision for designing dynamically reconfigurable systems

M.D. Santambrogio, C. Pilato, D. Pnevmatikatos, K. Papadimitriou, D. Stroobandt, D. Sciuto

International Conference on IC Design and Technology (ICICDT)

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A framework for effective exploitation of partial reconfiguration in dataflow computing

R. Cattaneo, X. Niu, C. Pilato, T. Becker, W. Luk, M.D. Santambrogio

International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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A flexible interconnection structure for reconfigurable FPGA dataflow applications

G. Durelli, A.A. Nacci, R. Cattaneo, C. Pilato, D. Sciuto, M.D. Santambrogio

Reconfigurable Architectures Workshop (RAW)

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D-RECS: A complete methodology to implement Self Dynamic Reconfigurable FPGA-based systems

F. Cancare, C. Pilato, A. Cazzaniga, D. Sciuto, M.D. Santambrogio

International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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Ant colony optimization for mapping, scheduling and placing in reconfigurable systems

F. Ferrandi, P.L. Lanzi, C. Pilato, D. Sciuto, A. Tumeo

NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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A2B: An integrated framework for designing heterogeneous and reconfigurable systems

C. Pilato, R. Cattaneo, G. Durelli, A.A. Nacci, M.D. Santambrogio, D. Sciuto

NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Runtime adaptation on dataflow HPC platforms

R. Cattaneo, C. Pilato, M. Mastinu, O. Kadlcek, O. Pell, M.D. Santambrogio

NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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SMASH: A heuristic methodology for designing partially reconfigurable MPSoCs

R. Cattaneo, C. Pilato, G.C. Durelli, M.D. Santambrogio, D. Sciuto

International Symposium on Rapid System Prototyping (RSP)

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Dataflow computing with polymorphic registers

C. Ciobanu, G. Gaydadjiev, C. Pilato, D. Sciuto

International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)

C

A simulation-based framework for the exploration of mapping solutions on heterogeneous MPSoCs

A. Miele, C. Pilato, D. Sciuto

International Journal of Embedded and Real-Time Communication Systems

J

2012

FASTER: Facilitating analysis and synthesis technologies for effective reconfiguration

D. Pnevmatikatos, T. Becker, A. Brokalakis, K. Bruneel, G. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, O. Pell, C. Pilato, M. Robart, M.D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman

Euromicro Conference on Digital System Design (DSD)

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Novel design methods and a tool flow for unleashing dynamic reconfiguration

K. Papadimitriou, C. Pilato, D. Pnevmatikatos, M.D. Santambrogio, C. Ciobanu, T. Todman, T. Becker, T. Davidson, X. Niu, G. Gaydadjiev, W. Luk, D. Stroobandt

IEEE International Conference on Computational Science and Engineering (CSE)

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On the automatic integration of hardware accelerators into FPGA-based embedded systems

C. Pilato, A. Cazzaniga, G. Durelli, A. Otero, D. Sciuto, M.D. Santambrogio

International Conference on Field Programmable Logic and Applications (FPL)

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An open-source design and validation platform for reconfigurable systems

A. Bonetto, A. Cazzaniga, G. Durelli, C. Pilato, D. Sciuto, M.D. Santambrogio

International Conference on Field Programmable Logic and Applications (FPL)

C

TaBit: A framework for task graph to bitstream generation

A. Bonetto, A. Cazzaniga, G.C. Durelli, C. Pilato, D. Sciuto, M.D. Santambrogio

International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS)

C

Smart technologies for effective reconfiguration: The FASTER approach

M.D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. Pilato, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga, G.C. Durelli, D. Sciuto

International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

C

Automatic run-time manager generation for reconfigurable MPSoC architectures

G. Durelli, C. Pilato, A. Cazzaniga, D. Sciuto, M.D. Santambrogio

International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC)

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On the development of a runtime reconfigurable multicore system-on-chip

A. Cazzaniga, G. Durelli, C. Pilato, D. Sciuto, M.D. Santambrogio

Euromicro Conference on Digital System Design (DSD)

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An automated framework for the simulation of mapping solutions on heterogeneous MPSoCs

A. Miele, C. Pilato, D. Sciuto

International Symposium on System on Chip (SoC)

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2011

A runtime adaptive controller for supporting hardware components with variable latency

C. Pilato, V.G. Castellana, S. Lovergine, F. Ferrandi

NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

C

Combined architecture and hardening techniques exploration for reliable embedded system design

C. Bolchini, A. Miele, C. Pilato

ACM Great Lakes Symposium on VLSI (GLSVLSI)

C

A design methodology for the automatic sizing of standard-cell libraries

C. Pilato, F. Ferrandi, D. Pandini

ACM Great Lakes Symposium on VLSI (GLSVLSI)

C

Synaptic project: Regularity applied to enhance manufacturability and yield at several abstraction levels (invited paper)

M. Elhoj, A. Reis, R. Ribas, F. Ferrandi, C. Pilato, F. Moll, M. Miranda, P. Dobrovolny, N. Woolaway, A. Grasset, P. Bonnot, G. Desoli, D. Pandini

Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms (ERDIAP)

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Evaluating static CMOS complex cells in technology mapping

C. Pilato, F. Ferrandi, D. Pandini

Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms (ERDIAP)

C

2010

The hArtes CarLab: A new approach to advanced algorithms development for automotive audio

S. Cecchi, A. Primavera, F. Piazza, F. Bettarelli, E. Ciavattini, R. Toppi, J.G.F. Coutinho, W. Luk, C. Pilato, F. Ferrandi, V.M. Sima, K. Bertels

Audio Engineering Society Convention (AES)

C

HArtes: Hardware-software codesign for heterogeneous multicore platforms

K. Bertels, V.-M. Sima, Y. Yankova, G. Kuzmanov, W. Luk, G. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada, D. Sciuto, A. Michelotti

IEEE Micro

J

Ant colony heuristic for mapping and scheduling tasks and communications on heterogeneous embedded systems

F. Ferrandi, P.L. Lanzi, C. Pilato, D. Sciuto, A. Tumeo

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

J

Mapping and scheduling of parallel C applications with ant colony optimization onto heterogeneous reconfigurable MPSoCs

F. Ferrandi, C. Pilato, D. Sciuto, A. Tumeo

Asia and South Pacific Design Automation Conference (ASP-DAC)

C

A fast heuristic for extending standard cell libraries with regular macro cells

C. Pilato, F. Ferrandi, D. Pandini

IEEE Annual Symposium on VLSI (ISVLSI)

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2009

Mapping pipelined applications onto heterogeneous embedded systems: A Bayesian optimization algorithm based approach

A. Tumeo, M. Branca, L. Camerini, C. Pilato, P.L. Lanzi, F. Ferrandi, D. Sciuto

IEEE/ACM International Conference on Hardware/Software-Co-Design and System Synthesis (CODES+ISSS)

C

Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems

M. Branca, L. Camerini, F. Ferrandi, P.L. Lanzi, C. Pilato, D. Sciuto, A. Tumeo

Annual Genetic and Evolutionary Computation Conference (GECCO)

C

HW/SW methodologies for synchronization in FPGA

A. Tumeo, C. Pilato, G. Palermo, F. Ferrandi, D. Sciuto

ACM SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA)

C

Performance estimation for task graphs combining sequential path profiling and control dependence regions

F. Ferrandi, M. Lattuada, C. Pilato, A. Tumeo

IEEE/ACM International Conference on Formal Methods and Models for Co-Design (MEMOCODE)

C

Performance modeling of parallel applications on MPSoCs

M. Lattuada, C. Pilato, A. Tumeo, F. Ferrandi

International Symposium on System-on-Chip (SoC)

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2008

Improving evolutionary exploration to area-time optimization of FPGA designs

C. Pilato, A. Tumeo, G. Palermo, F. Ferrandi, P.L. Lanzi, D. Sciuto

Journal of Systems Architecture

J

A multi-objective genetic algorithm for design space exploration in high-level synthesis

F. Ferrandi, P.L. Lanzi, D. Loiacono, C. Pilato, D. Sciuto

IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

C

High-level synthesis with multi-objective genetic algorithm: A comparative encoding analysis

C. Pilato, D. Loiacono, F. Ferrandi, P.L. Lanzi, D. Sciuto

IEEE Congress on Evolutionary Computation (CEC)

C

Ant colony optimization for mapping and scheduling in heterogeneous multiprocessor systems

A. Tumeo, C. Pilato, F. Ferrandi, D. Sciuto, P.L. Lanzi

International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS)

C

2007

An evolutionary approach to area-time optimization of FPGA designs

F. Ferrandi, P.L. Lanzi, G. Palermo, C. Pilato, D. Sciuto, A. Tumeo

International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS)

C

Fitness inheritance in evolutionary and multi-objective high-level synthesis

C. Pilato, G. Palermo, A. Tumeo, F. Ferrandi, D. Sciuto, P.L. Lanzi

IEEE Congress on Evolutionary Computation (CEC)

C