About me

I will be serving as a TPC member at FPT 2022

I will be serving as PhD Forum Chair (DEC member) at DATE 2023.

I will be serving as Topic Chair at DATE 2023 (topic “System-Level Design Methodologies and High-Level Synthesis”).

New paper accepted at IEEE TCAD: Optimizing the Use of Behavioral Locking for High-Level Synthesis. This is a joint work with NYU.

I will be serving as a TPC member at ASPDAC 2023

I will be serving as Track Chair at CASES 2022 (topic ” “Architectures, Compilers, System-level Design”).

I will be the Program Chair of ICCD 2022.

I will organize a special session titled “Security during system level design: Small step or giant leap?” at DAC 2022.

I will be serving as a TPC member at ICCAD 2022

Two new papers accepted for presentation at DAC 2022: Designing ML-Resilient Locking at Register-Transfer Level (joint work with RWTH Aachen University, University of Calgary, and NYU) and ALICE: An Automatic Design Flow for eFPGA Redaction (joint work with University of Calgary, NYU, and University of Utah).

New paper accepted at MDPI Electronics: Dynamically-Tunable Dataflow Architectures based on Markov Queuing Models

I will be serving as a TPC member at CASES 2022

I will be serving as Tutorial Committee Member at SC 2022

New paper accepted for presentation at TACAS 2022: HOLL: Program Synthesis for Higher Order Logic Locking. This is a joint work with IIT Kanpur and NYU.

New paper accepted for presentation at DATE 2022: A Composable Design Space Exploration Framework to Optimize Behavioral Locking.

Together with Jeronimo Castrillon (TUD) and Christoph Hagleitner (IBM), we will be organizing a Workshop “Data-driven applications for industrial and societal challenges: Problems, methods, and computing platforms” at DATE 2022.

Our RTL locking ASSURE tool is now part of the IEEE CEDA DATC Robust Design Flow (RDF)

I will be serving as Track Chair at DAC 2022 (topic “RTL/Logic Level and High-level Synthesis”).

New paper accepted at the Journal of Integrated Circuits and Systems: A Survey on Domain-Specific Memory Architectures.

New paper accepted for presentation at HPC-FPGA 2021: From Domain-Specific Languages to Memory-Optimized Accelerators for Fluid Dynamics. This is a joint work with TU Dresden.

Together with Francesco Regazzoni (USI), Katerina Slaninova (IT4I), and Antonella Galizia (CIMA), we will be organizing the PhD Summer School “Extreme-scale big data analytics and scientific computing on heterogeneous platforms” at Lake Como in 2022.

New paper accepted for presentation at ICCAD 2021: Exploring eFPGA-based Redaction for IP Protection. This is a joint work with New York University and University of Utah.

New paper accepted at ACM TECS and for presentation at CASES 2021: CICERO: A Domain-Specific Architecture for Efficient Regular Expression Matching.

Together with Francesco Regazzoni (USI), Jeronimo Castrillon (TU Dresden), and Antonella Galizia (CIMA), we will be organizing the EVEREST Workshop on Design and Programming High-performance, distributed, reconfigurable and heterogeneous platforms for extreme-scale analytics at HIPEAC 2022.

I will be serving as Topic Co-Chair at DATE 2022 (topic “System-Level Design Methodologies and High-Level Synthesis”).

New paper accepted at IEEE TVLSI: ASSURE: RTL Locking Against an Untrusted Foundry. This is a joint work with New York University.

I will be serving as a TPC member at ICCAD 2021

I will be lead guest editor of the ACM TODAES special issue on High-Level Synthesis for FPGA: Next-Generation Technologies and Applications. The GE team includes Zhenman Fang (Simon Fraser University), Yuko Hara-Azumi (Tokyo Institute of Technology), and Jim Hwang (Xilinx, Inc).

New paper accepted for presentation at DAC 2021: Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks. This is a joint work with New York University and New York University Abu Dhabi.

I will give a keynote at RAPIDO 2021 (HiPEAC Workshop).